1. Field of the Invention
The present invention generally concerns the control of a phase locked loop (PLL), and in more particular concerns the simultaneous control of frequency and amplitude in a PLL.
2. Background Information
Amplitude control of an oscillator over process, temperature, and power supply variations is a challenging task in PLL design. Uncontrolled oscillation amplitude can be a source of additional jitter due to changing operating points and cyclostationary device noises. Another application that requires amplitude control in PLLs is the master-slave tuning in on-chip filters. Oscillation amplitude of the PLL should match with the signal amplitude processed in the filter to avoid distortion that causes frequency errors. However, active amplitude compensation incorporated into a PLL can be a major problem of stability. Consider a gm-C (transconductance-Cell) based relaxation type oscillator. The loop introduced to control amplitude interferes with the main phase/frequency locking loop. The mechanism that adjusts the amplitude, i.e., the current of the negative gm load of the oscillator where the negative gm load is used to compensate for resistive losses, initiates the oscillation cycle as well as sets the oscillation amplitude, thereby imposing an inverse force that causes the two loops that fight each other, wherein precise control of one of the loops has an adverse effect on the control of the other loop. The traditional solution to minimize the problem is to maximize the difference between time constants governing the amplitude and phase/frequency locking loops. Basically, the amplitude loop should be slowed down by using large component values, such as huge capacitors, which consumes more area and power than desired. Still, the system should be overdesigned to have enough margin to accommodate not only the environmental variables, but also component values especially for large time constants.